Systems having a resistive memory device

A system comprising:

• a controller configured to control the system;
• and
• a resistive memory device coupled to the controller, the memory device comprising:
• an array of resistive memory cells comprising a plurality of resistive memory cells organized in rows and columns wherein each column of memory cells is coupled to a corresponding data line of a plurality of data lines and each row of memory cells is coupled to a corresponding access line of a plurality of access lines;
• sense circuitry coupled to the access lines of the plurality of access lines and configured to read data stored in the array of resistive memory cells;
• row decoders coupled to the data lines of the plurality of data lines and configured to bias a selected data line with programming pulses during a programming operation;
• and
• control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits that are both to be programmed are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells of the plurality of resistive memory cells coupled to the selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data bits wherein the pairs of adjacent memory cells comprise memory cells that have a back-to-back relationship separated by a first distance along an axis in a direction of the selected data line.

A system comprising:

• a controller configured to control the system;
• and
• a resistive memory device coupled to the controller, the memory device comprising:
• an array of resistive memory cells comprising a plurality of resistive memory cells organized in rows and columns wherein each column of memory cells is coupled to a corresponding data line of a plurality of data lines and each row of memory cells is coupled to a corresponding access line of a plurality of access lines;
• sense circuitry coupled to the access lines of the plurality of access lines and configured to read data stored in the array of resistive memory cells;
• row decoders coupled to the data lines of the plurality of data lines and configured to bias a selected data line with programming pulses during a programming operation;
• and
• control circuitry configured to build a data word from remapped data bits from a received data word by changing a bit order of the received data word such that pairs of data bits that are both to be programmed are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells of the plurality of resistive memory cells coupled to the selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data bits wherein the pairs of adjacent memory cells comprise memory cells that have a back-to-back relationship separated by a first distance along an axis in a direction of the selected data line;
• wherein programming the built data word to memory cells of the plurality of resistive memory cells comprises changing a resistance of a resistance variable material for each memory cell of the plurality of resistive memory cells to be programmed.