Resistance change memory cell circuits and methods
AssigneeRambus Inc.
InventorBrent Haukness
Life of this patent
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Abstract
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
Claims21
1-20. (canceled)
A method of reading a state of a resistive change memory element of an integrated circuit device, the method comprising:
- generating a reference current;
- during a reading of the state of the resistive change memory element, biasing an access transistor coupled to the resistive change memory element to establish a bias of the access transistor;
- and,
- during a reading of the state of the resistive change memory element, using a current mirror to establish from the reference current, a limited current that flows through the resistive change memory element.
An integrated circuit, comprising:
- at least one memory cell having an access transistor coupled to a resistive change memory element;
- a reference current generator;
- and,
- a word line driver circuit to receive, during a read operation, a reference current from the reference current generator, to generate a bias, and to bias the access transistor during the read operation such that a current that flows through the access transistor during the read operation is limited.
A memory device comprising:
- memory cells each having a resistance which is changeable from at least a first resistance to a second resistance;
- a first voltage generating circuit to generate a voltage to apply to a terminal of at least one of the memory cells;
- and
- a second voltage generating circuit to generate a bias voltage to be applied to a control node of the of memory cells, the bias voltage determining an operating point of a transistor that establishes a current to flow through the transistor, the current to flow through at least one variable resistive device of the memory cell to determine whether the resistance of the at least one variable resistive device is a one of the first resistance to the second resistance while being limited by the operating point of the transistor.
Dependencies are inferred from the claim text.