Apparatuses including memory cells and methods of operation of same

An apparatus, comprising:

• a memory cell including a storage element;
• a first memory access line coupled to the memory cell;
• a second memory access line coupled to the memory cell;
• a first access line driver coupled to the first memory access line;
• a second access line driver coupled to the second memory access line;
• and
• a control logic configured to control the first and second access line drivers to:
• provide a programming pulse having a first portion and a second portion across the memory cell to program a logic state to the storage element,
• provide a read pulse in a first polarity across the memory cell to determine the logic state of the memory cell, and
• wherein the first portion includes at least one of a ramp, a staircase, and a plurality of pulses.

A method comprising:

• applying a programming pulse across a memory cell in a first polarity, wherein the programming pulse is configured to program a logic state to a memory element of the memory cell;
• and
• applying a read pulse across the memory cell in a second polarity, wherein the read pulse is configured to determine the logic state of the memory element, and
• wherein the logic state programmed to the memory element is based, at least in part, on a magnitude of the programming pulse, wherein the magnitude is a current magnitude or a voltage magnitude.

A method comprising:

• applying a first portion of a programming pulse in a first polarity across a memory cell;
• applying a second portion of a programming pulse in a second polarity across the memory cell;
• and
• applying a read pulse in the first polarity across the memory cell wherein the read pulse is configured to determine a logic state of the memory cell,
• wherein the first portion of the programming pulse is configured to program a logic state to a memory element of the memory cell.