Electronic device
AssigneeSK hynix Inc.
InventorKi-Won Lee
Life of this patent
Estimating the term…
Abstract
An electronic device including a semiconductor memory The semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.
Claims22
An electronic device including a semiconductor memory, the semiconductor memory comprising:
- one or more resistive storage cells each structured to exhibit different resistance values for storing data;
- a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series;
- a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell;
- and
- a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block.
An electronic device including a semiconductor memory, the semiconductor memory comprising:
- a plurality of bit lines and a plurality of source lines;
- a plurality of resistive storage cells coupled between a corresponding bit line and a corresponding source line among the plurality of bit lines and the plurality of source lines;
- a plurality of reference bit lines and a plurality of reference source lines;
- a plurality of reference resistance blocks coupled between a corresponding reference bit line and a corresponding reference source line among the plurality of reference bit lines and the plurality of reference source lines, and each including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series;
- a plurality of data sensing blocks each comparing a read current flowing through a corresponding bit line among the plurality of bit lines and a reference current flowing through a corresponding reference bit line among the plurality of reference bit lines to determine data stored in a resistive storage cell selected among a plurality of resistive storage cells coupled to the corresponding bit line;
- and
- a reference resistance adjustment block coupled to the reference resistance blocks and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust resistance values of the reference resistance blocks.
Dependencies are inferred from the claim text.