Multi-port memory and semiconductor device

A multi-port memory comprising:

• a memory array including a plurality of memory cells and a plurality of word lines;
• a control circuit for generating a start signal based on an input clock signal;
• an address control circuit including a plurality of ports, to activate one of the word lines by decoding one of a plurality of address signals input from the ports;
• and
• a data input/output circuit for writing or reading data by selecting one of the memory cells coupled to the activated word line, based on an output from the address control circuit,
• wherein the control circuit includes:
• a pulse signal generation unit that generates a pulse signal;
• a start signal generation unit that generates a start signal in response to an output of the pulse signal generation unit;
• and
• a delay circuit that generates a delay signal to delay the start signal,
• wherein the pulse signal generation unit includes a first pulse signal generator circuit that generates a first pulse signal in response to an input of a clock signal,
• wherein the start signal generation unit includes a first latch circuit that sets the first start signal to a first state and holds this state in response to generation of the first pulse signal, and then resets the first start signal to a second state in response to a first delayed signal that is obtained by delaying the first start signal by the delay circuit,
• wherein the pulse signal generation unit further includes a second pulse signal generator circuit that generates a second pulse signal in response to the input of the first delayed signal, and
• wherein the first latch circuit sets a second start signal to the first state and holds this state in response to generation of the second pulse signal, and then resets the second start signal to the second state in response to a second delayed signal obtained by delaying the second start signal by the delay circuit.