Memory Device Comprising An Electrically Floating Body Transistor

A memory cell comprising:

• an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said electrically floating body region;
• a drain region comprising said second conductivity type in physical contact with said electrically floating body region and spaced apart from said source line region;
• a first charge injector region, wherein said first charge injection region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region and said drain region;
• a second charge injector region, wherein said second charge injection region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region, said drain region, and said first charge injector region;
• a gate region positioned in between said source line region and said drain region, the gate region being positioned between said first charge injector region and said second charge injector region;
• and
• wherein said electrically floating body region is configured to have more than one stable state through an application of a bias on said first and second charge injector regions.