Dpu architecture
AssigneeSamsung Electronics Co., Ltd.
InventorsShaungchen LI, Dimin NIU, Krishna MALLADI, Hongzhong ZHENG
Life of this patent
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Abstract
A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.
Claims20
A dynamic random access memory (DRAM) processing unit (DPU), comprising:
- at least one computing cell array comprising a plurality of DRAM-based computing cells arranged in an array having at least one column, the at least one column comprising at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows;
- and
- a controller coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.
A dynamic random access memory (DRAM) processing unit (DPU), comprising:
- at least one computing cell array comprising a plurality of DRAM-based computing cells arranged in an array having at least one column, the at least one column comprising at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows;
- at least one data cell array comprising at least one DRAM-based memory cell arranged in at least one column;
- and
- a controller coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation and coupled to the at least one data cell array to perform a memory operation.
A dynamic random access memory (DRAM) processing unit (DPU), comprising:
- at least one computing cell array comprising a plurality of DRAM-based computing cells arranged in an array having at least one column, the at least one column comprising at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows;
- at least one stochastic computing cell array comprising a plurality of DRAM-based stochastic computing cells arranged in an array having at least one column, the at least one column comprising at least three rows of DRAM-based stochastic computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows;
- and
- a controller coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation and coupled to the at least one stochastic computing cell array to perform a stochastic logic operation.
Dependencies are inferred from the claim text.