Semiconductor memory
AssigneeLapis Semiconductor Co., Ltd.
InventorTakashi YAMADA
Life of this patent
Estimating the term…
Abstract
A semiconductor memory includes j×k first memory cells, j upper bit lines, (½)j sense amplifiers, j×k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j×m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.
Claims10
A semiconductor memory having a first memory region and a second memory region, comprising:
- j×k first memory cells arranged in j rows and k columns in the first memory region, j being a positive even number, k being a natural number;
- j upper bit lines each connected to the k first memory cells of a corresponding one of the j rows;
- (½)j sense amplifiers each connected to two of the j upper bit lines;
- j×k lower first bit lines connected respectably to the j×k first memory cells, each of k of the j×k lower first bit lines connected to memory cells of one of the j rows being connected to a corresponding one of the j upper bit lines;
- k first word lines each connected to the j first memory cells of a corresponding one of the k columns;
- k pairs of plate lines, each pair having a first plate line and a second plate line, each said first plate line being connected to odd-numbered first memory cells of a corresponding one of the k columns, each said second plate line being connected to even-numbered first memory cells of a corresponding one of the k columns;
- a pair of discharge signal lines having
- a first discharge signal line, and
- a second discharge signal line respectively connecting the two of the j upper bit lines in each sense amplifier to a prescribed potential;
- j×m second memory cells arranged in j rows and m columns in the second memory region, the m second memory cells of a same row being connected to a corresponding one of the j upper bit lines, m being a natural number;
- j lower second bit lines each corresponding to one of the j upper bit lines;
- m second word lines each connected to the j second memory cells of a corresponding one of the m columns;
- m third plate lines each connected to the j second memory cells of a corresponding one of the m columns;
- and
- j shield lines each provided at positions respectively corresponding to the j upper bit lines and respectively adjacent to the j lower second bit lines, which are parallel to one another.
A semiconductor memory having a first memory region and a second memory region, comprising:
- j×k first memory cells arranged in j rows and k columns in the first memory region, j being a positive even number, k being a natural number;
- j upper bit lines each connected to the k first memory cells of a corresponding one of the j rows;
- (½)j sense amplifiers each connected to two of the j upper bit lines;
- j×k lower first bit lines connected respectably to the j×k first memory cells;
- k pairs of word lines, each pair having a first word line and a second word line, each said first word line being connected to odd-numbered first memory cells of a corresponding one of the k columns, each said second word line being connected to even-numbered first memory cells of the corresponding one of the k columns;
- a pair of discharge signal lines having
- a first discharge signal line, and
- a second discharge signal line selectively connecting the two of the j upper bit lines in each sense amplifier to a prescribed potential;
- j×m second memory cells arranged in j rows and m columns in the second memory region, the m second memory cells in a same row being connected to a corresponding one of the j upper bit lines, m being a natural number;
- j lower second bit lines each corresponding to one of the j upper bit lines;
- m third word lines each connected to the j second memory cells of a corresponding one of the m columns;
- and
- j shield lines each provided at positions respectively corresponding to the j upper bit lines and respectively adjacent to the j lower second bit lines, which are parallel to one another.
Dependencies are inferred from the claim text.