Smart cache design to prevent overflow for a memory device with a dynamic redundancy register

A memory device for storing data, the memory device comprising:

• a memory bank comprising a plurality of addressable memory cells of row and bit lines and further configured in a plurality of segments wherein each segment contains N rows per segment and wherein words are addressed by a common row line and a plurality of bit lines and wherein said memory bank is characterized by having a prescribed word error rate, E, and wherein the memory bank comprises a total of B entries;
• a pipeline comprising M pipestages and configured to process read operations and write operations of a first plurality of data words addressed to a given segment of said memory bank;
• and
• a cache memory comprising Y number of entries, said cache memory associated with said given segment of said memory bank and wherein said cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said given segment of said memory bank or is to be re-written into said given segment of said memory bank, and wherein said Y number of entries is based on said M, said N and said prescribed word error rate, E, to prevent overflow of said cache memory.

A method of writing data within a memory device, the method comprising:

• processing write operations using a pipeline wherein said pipeline is operable to process said write operations to write data to a memory bank, wherein said processing comprises transferring write operations to a cache memory that require one of:
• write verification;
• and subsequent write processing;
• storing a write operation in a vacant entry of said cache memory that requires one of:
• write verification;
• and subsequent write processing through said pipeline;
• removing a write operation from said cache memory that write verifies;
• and
• removing a write operation from said cache memory that is re-written to said memory bank, and
• wherein said memory bank comprises a plurality of addressable memory cells of N word row lines wherein words are addressed by a common word row line and a plurality of bit column lines, wherein said memory bank is characterized by having a prescribed word error rate, E, and wherein the memory bank comprises a total of B entries, and
• wherein said pipeline comprises M pipestages, and
• wherein said cache memory comprises Y number of entries, wherein said Y number of entries is based on said M, said N and said prescribed word error rate, E, to prevent overflow of said cache memory.