Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers

A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

• an input register operable to receive a first data word and an associated address to be written into a memory bank;
• a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register in a first part of the first clock cycle, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address;
• and
• a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register in a second part of the first clock cycle, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address, and further wherein a second data word is input into the first write register in the second part of the first clock cycle subsequent to writing the first data word into the second write register from the first write register, wherein the second pipe-stage follows the first pipe-stage.

A system for performing a write operation in a memory device, the system comprising:

• a memory pipeline;
• a memory bank coupled to the memory pipeline;
• and
• a first level dynamic redundancy register, wherein the memory pipeline comprises:
• an input register operable to receive a first data word and an associated address to be written into the memory bank;
• a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register in a first clock cycle, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address;
• and
• a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register in a second clock cycle, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address, and further wherein a second data word is input into the first write register in the second clock cycle subsequent to writing the first data word into the second write register from the first write register, wherein the second pipe-stage follows the first pipe-stage.