Memory device with a dual y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

A memory device for storing data, the memory device comprising:

• a memory bank comprising a memory array of addressable memory cells, wherein said addressable memory cells comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;
• a pipeline configured to process read and write operations addressed to said memory bank, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage;
• a row decoder circuit coupled to said memory array for decoding a row portion of a memory address and for asserting a row line of said memory array;
• and
• a column multiplexer circuit coupled to said memory array and operable to simultaneously multiplex based on two column portions of memory addresses and, based thereon with said row portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array,
• wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.

A method of accessing a memory device, said method comprising:

• processing read and write operations addressed to a memory bank using a pipeline, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage and wherein further said memory bank comprises a memory array of addressable memory cells that comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;
• decoding a row portion of a memory address and asserting a row line of said memory array using a row decoder circuit coupled to said memory array;
• and
• simultaneously multiplexing column lines of said memory array based on two column portions of memory addresses and, based thereon with said row portion, simultaneously writing a value and reading a value associated with two separate memory cells of said memory array using a column multiplexer circuit coupled to said memory array, and
• wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.