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US 2018/0122443 A1Published application
Apparatuses and methods involving accessing distributed sub-blocks of memory cells
AssigneeMicron Technology, Inc.
InventorToru Tanzawa
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.
Claims23
(canceled)
A method, comprising:
- accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time, wherein the first and second sub-blocks of memory cells are part of a first block of memory cells of multiple blocks of memory cells of a memory array,
- wherein the first and second sub-blocks within the block are enabled to be accessed simultaneously, and wherein the memory cells in a second block of memory cells are not enabled to be accessed when memory cells of the first block are being accessed;
- and
- wherein the first sub-block of the block of memory cells and the second sub-block of the block of memory cells are not in the same row or the same column of the block of memory cells.
1 more element
A method comprising:
- receiving a memory request in an apparatus;
- and
- executing the memory request in the apparatus, wherein the executing comprises:
- enabling multiple sub-blocks in a block of memory cells to be accessed simultaneously in response to the memory request, while leaving other sub-blocks in the block of memory cells disabled for access;
- wherein the memory array comprises rows and columns of sub-blocks of memory cells, and
- wherein the enabled sub-blocks are each in a row and column that does not include another enabled sub-block;
- accessing first data in a first sub-block of memory cells of the block of memory cells;
- and
- accessing second data in a second sub-block of memory cells of the block of memory cells simultaneously with accessing the first data.
6 more elements
A 3D memory device comprising:
- in a stack an array multiple arrays of memory cells, each of the stacked arrays having multiple sub-blocks of memory cells, accessing multiple sub-blocks of memory cells in each of multiple arrays simultaneously;
- wherein the simultaneously accessed sub-blocks in a first array are in different rows and columns from one another;
- and
- wherein the simultaneously accessed sub-blocks in a second array are in different rows and columns from one another.
1 more element
Dependencies are inferred from the claim text.