Semiconductor memory devices and memory systems including the same

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
• a control logic circuit configured to control access to the memory cell array in response to a command and an access address received from a memory controller;
• and
• a timing control circuit configured to:
• generate first control signals to control voltage levels of the word-lines in response to operation control signals provided from the control logic circuit;
• enable a first word-line of the plurality of word-lines in response to a first command received from the memory controller, the first word-line being selected in response to the access address;
• and
• disable the first word-line internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses;
• wherein the reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and
• wherein the reference time interval corresponds to a time interval equal to or greater than a row active time (tRAS) interval of the semiconductor memory device.

A semiconductor device comprising:

• at least one semiconductor memory device comprising a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines, in which the at least one semiconductor memory device includes a control logic circuit configured to disable internally at least a first word-line of the plurality of word-lines;
• a memory controller including a central processing unit, a command queue, and a command generator, the central processing unit is configured to:
• monitor a status of the command queue, and control the command generator to apply a disable command to disable externally a first word-line of the at least one semiconductor memory device when a write command is not present in the command queue during a predetermined time interval after an active command is applied to the first word-line of the at least one semiconductor memory device,
• wherein the predetermined time interval corresponds to a time interval equal to or greater than a row active time (tRAS) interval of the semiconductor memory device.