Methods and apparatuses for command shifter reduction
AssigneeMicron Technology, Inc.
InventorsDebra Bell, Kallol Mazumder
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.
Claims20
An apparatus, comprising:
- an encoder circuit configured to encode a command and provide an encoded command and a preceding code indicative of the encoded command, the preceding code indicative of the encoded command in clock cycles between the encoded command and another encoded command;
- and
- a decoder circuit configured to decode at least the encoded command and to provide a decoded command indicative of the command.
An apparatus comprising:
- a first decoder circuit including a first output node and a second output node that is separated from the first output node, the first decoder circuit being configured to provide a first active signal at the first output node responsive to decoding a first command, and the first decoder circuit being further configured to provide a second active signal at the second output node responsive to decoding a second command;
- an encoder circuit including a first input node coupled to the first output node and a second input node coupled to the second output node, the encoder circuit further including a common output node, the encoder circuit being configured to provide a first encoded signal at the common output node based, at least in part, on the first active signal, and the encoder circuit being further configured to provide a second encoded signal at the common output node based, at least in part, on the second active signal;
- and
- a second decoder circuit including a common input node coupled to the common output node, the second decoder circuit further including a third output node and a fourth output node that is separated from the third output node, the second decoder circuit being configured to provide a first decoded signal at the third output node based, at least in part, on the first encoded signal, and the second decoder circuit being further configured to provide a second decoded signal at the fourth output node based, at least in part, on the second encoded signal.
The apparatus of claim 16, wherein the second decoder circuit provides the first decoded signal and the second decoded signal at the third output node and the fourth output node, respectively, in a time-series manner.
A method, comprising:
- encoding a command based on command type to generate an encoded command;
- decoding the encoded command to generate a decoded command associated with the command type;
- and
- providing the decoded command to perform a memory operation corresponding to the command type.
Dependencies are inferred from the claim text.