US 2018/0122438 A1Published application

Clocked commands timing adjustments in synchronous semiconductor integrated circuits

AssigneeIntegrated Silicon Solution, Inc.

InventorsMatthew Manning, Steven Eaton

Life of this patent

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Abstract

A clock timing adjust circuit is incorporated in a clocked integrated circuit to detect an input clock frequency and to adjust the timing latency of an internal control signal for accessing a memory element in the clocked integrated circuit. The clock timing adjust circuit introduces an adjustable timing latency to an internal control signal derived from the command signal. The clock timing adjust circuit operates to adjust the timing latency of the control signal to cause clock based operations to either be advanced or delayed by one or more clock cycles in response to the clock frequency detection. In one embodiment, the clock timing adjust circuit includes a clock frequency detect circuit and a latency adjust circuit. The clock timing adjust circuit can operate at both high and low clock frequencies to ensure that undesired data collision events are obviated without introducing unnecessary delays.

Claims18

Dependent claims

A clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit, the clocked integrated circuit comprising:

a clock frequency detect circuit receiving the input clock signal and generating a clock detect output signal, the clock detect output signal having a first logical state in response to the clock frequency being below a frequency threshold and having a second logical state in response to the clock frequency being at or above a frequency threshold;
and
a latency adjust circuit receiving the input clock signal, the command signal and the clock detect output signal, the latency adjust circuit generating a timing adjusted control signal being the command signal delayed by a first timing latency, the first timing latency comprises one or more clock periods of the input clock signal, wherein the latency adjust circuit adjusts the first timing latency in response to the clock detect output signal.

Dependencies are inferred from the claim text.

Facts

Application: 15/337,990Filed 28 Oct 2016
Published: 3 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H04L 7/0008
Arrangements for synchronising receiver with transmitter: synchronisation information channels, e.g. clock distribution lines
G11C 2207/2272
Control and timing of internal memory operations: latency related aspects