Memory decoding system

A memory decoding system, comprising:

• a memory decoding reference current module, comprising:
• a first reference current unit connected to one end of a second reference bit line;
• a second reference current unit connected to one end of a first reference bit line;
• a third reference current unit connected to one end of a third reference bit line;
• a first reference NMOS transistor, a source of which is connected to the second reference bit line;
• a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor;
• and
• a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level, wherein:
• the first reference bit line and the third reference bit line are configured as un-selected reference bit lines;
• and
• the second reference bit line is configured as a selected reference bit line;
• another end of the first reference bit lines and another end of the third reference bit line are configured to output signals;
• and
• a drain of the second reference NMOS transistor is configured to output signal.