Memory device and memory system including the same

A memory system comprising:

• a system controller;
• and
• a memory device controlled by the system controller, the memory device comprising:
• a first memory rank comprising at least one volatile memory chip;
• at least one data buffer configured to buffer data being at least one of input to and output from each of the at least one volatile memory chip;
• and
• a second memory rank comprising at least one non-volatile memory chip,
• wherein the memory device is configured to, upon receiving an event signal from the system controller, perform training between the first memory rank and the second memory rank without training data passing through the data buffer, to determine a delay of a strobe signal.

A method of determining a delay offset amount applied to a data strobe signal in a memory device comprising a first memory rank and a second memory rank, the method comprising:

• providing, by a memory controller, a training command to the second memory rank;
• based on the training command, activating a training functionality of the second memory rank;
• transmitting, from the first memory rank to the second memory rank, training data and a data strobe signal;
• determining, by the second memory rank, whether the training data is correctly detected based on the data strobe signal;
• and
• in response to a determination that the training data is incorrectly detected based on the data strobe signal, adjusting the delay offset amount applied to the data strobe signal.