Multiple register memory access instructions, processors, methods, and systems

A method performed by a processor, the method comprising:

• storing a plurality of cache lines in a cache of the processor;
• storing data in a plurality of general purpose registers of the processor;
• storing a first 128-bit data in a first source 128-bit packed data register;
• storing a second 128-bit data in a second source 128-bit packed data register;
• fetching a store to memory instruction with an instruction fetch unit of the processor;
• decoding the store to memory instruction, the store to memory instruction having a first field specifying the first source 128-bit packed data register, having a second field specifying the second source 128-bit packed data register, and indicating a starting memory location in a memory at which to store data;
• and
• performing a store to memory operation, in response to the decoded store to memory instruction, the store to memory operation including:
• storing the first 128-bit data from the first source 128-bit packed data register to the memory starting at the indicated starting memory location;
• and
• storing the second 128-bit data from the second source 128-bit packed data register to the memory at a location adjacently after the first 128-bit data.

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a set of instructions, including a store to memory instruction, the set of instructions if processed by a machine to cause the machine to perform operations comprising to:

• store a plurality of cache lines in a cache;
• store data in a plurality of general purpose registers;
• store a first 128-bit data in a first source 128-bit packed data register;
• and
• store a second 128-bit data in a second source 128-bit packed data register;
• and
• the store to memory instruction if processed by the machine to cause the machine to perform operations comprising to:
• decode the store to memory instruction, the store to memory instruction having a first field to specify the first source 128-bit packed data register, having a second field to specify the second source 128-bit packed data register, and to indicate a starting memory location in a memory at which to store data;
• and
• perform a store to memory operation, in response to the decoded store to memory instruction, the store to memory operation to:
• store the first 128-bit data from the first source 128-bit packed data register to the memory starting at the indicated starting memory location;
• and
• store the second 128-bit data from the second source 128-bit packed data register to the memory at a location adjacently after the first 128-bit data.