High speed level shifter for high voltage applications
AssigneeTexas Instruments Incorporated
InventorsRavikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Sandeep Kesrimal Oswal
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Abstract
The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.
Claims20
A level shifter comprising:
- a first logic block configured to receive an input signal and configured to generate a primary pulsed input;
- a first transistor coupled between the first logic block and a first node, a gate terminal of the first transistor configured to receive the primary pulsed input;
- a latch coupled to the first node and a second node;
- a second logic block configured to receive the input signal and configured to generate a secondary pulsed input;
- and
- a second transistor coupled between the second logic block and the second node, a gate terminal of the second transistor configured to receive the secondary pulsed input.
A method comprising:
- generating a primary pulsed input in response to an input signal;
- activating a first transistor when the primary pulsed input is at logic high;
- generating a secondary pulsed input in response to the input signal;
- inactivating a second transistor when the secondary pulsed input is at logic low;
- transitioning a first node from a first voltage level to a second voltage level;
- and
- storing the first voltage level and the second voltage level in a latch coupled to the first node and a second node.
An ultrasound system comprising a transmitter, the transmitter further comprising:
- a level shifter configured to receive an input signal and configured to generate an output signal;
- a driver coupled to the level shifter and configured to generate a drive signal in response to the output signal;
- and
- a main transistor whose gate terminal is coupled to the driver, whose source terminal is coupled to a voltage supply source and whose drain terminal is coupled to a transducer, wherein the level shifter further comprising:
- a first logic block configured to receive an input signal and configured to generate a primary pulsed input;
- a first transistor coupled between the first logic block and a first node, a gate terminal of the first transistor configured to receive the primary pulsed input;
- a latch coupled to the first node and a second node;
- a second logic block configured to receive the input signal and configured to generate a secondary pulsed input;
- and
- a second transistor coupled between the second logic block and the second node, a gate terminal of the second transistor configured to receive the secondary pulsed input.
Dependencies are inferred from the claim text.