Display device
AssigneeSamsung Display Co., Ltd.
InventorsWON JIN SEO, Sung-In Kang, Hee-Jeong Seo, Jun Pyo Lee
Life of this patent
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Abstract
A display device may include: a plurality of pixels; a gate driver that receives clock signals and generates and applies a plurality of gate signals to a respective plurality of gate lines connected to the plurality of pixels; and a clock signal driver. The clock signal driver may output the clock signals and receive feedback clock signals derived from the clock signals, compare the feedback clock signals, and control amplitudes of the clock signals so that an amplitude difference between the feedback clock signals is less than a threshold.
Claims20
A display device comprising:
- a plurality of pixels;
- a gate driver configured to generate and apply a plurality of gate signals to a respective plurality of gate lines connected to the plurality of pixels, the gate signals being generated by using clock signals received by the gate driver;
- and
- a clock signal driver configured to output the clock signals to and receive feedback clock signals derived from the clock signals, compare the feedback clock signals, and control amplitudes of the clock signals so that an amplitude difference between the feedback clock signals is less than a threshold.
A display device comprising:
- clock lines carrying different respective clock signals, for application to different respective gate lines;
- a gate driver connected to the clock lines and configured to use the clock signals to generate and apply gate signals to respective gate lines connected to pixels;
- and
- a clock signal driver configured to output the clock signals to a first region of the clock lines, receive feedback clock signals flowing from a second region of the clock lines, compare current or voltage levels between the feedback clock signals, and control amplitudes of the outputted clock signals so that a current or voltage level difference between the feedback clock signals is less than a threshold.
A display device comprising:
- a plurality of pixels;
- a clock signal driver configured to output a plurality of clock signals;
- and
- a gate driver configured to use the clock signals to generate and apply a plurality of gate signals to a plurality of gate lines connected to the plurality of pixels;
- wherein the clock signal driver includes:
- a memory configured to store a plurality of resistance selection values and to output, responsive to a resistor selection signal, a multiplexer (MUX) control signal based on one of the resistance selection values selected according to the resistor selection signal;
- a clock signal generator generating an output clock signal;
- a resistor bank including a plurality of resistors;
- and
- MUX circuitry routing the output clock signal to a clock line connected to the gate driver through any one among the plurality of resistors and a direct connection path, according to the MUX control signal.
Dependencies are inferred from the claim text.