Gate driver and display device using the same
AssigneeLG Display Co., Ltd.
InventorsHyelim JI, Yongseok PARK
Life of this patent
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Abstract
A gate driver and a display device using the same are disclosed. The gate driver includes a plurality of stages connected in a cascade connection manner, and each of the stages include a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal. Each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal. Each of the stages includes a first diode connected between the clock input and the first output terminal.
Claims20
A gate driver, comprising:
- a plurality of stages connected in a cascade connection manner, each of the stages including a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal,
- wherein each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal, and
- wherein each of the stages includes a first diode connected between the clock input and the first output terminal.
A display device comprising:
- a display panel in which data lines and gate lines are arranged in intersecting directions, and pixels are arranged in a matrix form;
- and
- a display driver configured to write data of an input image to the pixels, the display driver including a shift register having a plurality of stages connected in a cascade connection manner and configured to sequentially supply gate pulses to the gate lines, each of the stages including:
- a clock input configured to receive a shift clock signal;
- a first output terminal configured to supply a first output voltage to another stage;
- a second output terminal configured to supply a second output voltage to a gate line of the display panel;
- and
- a first diode connected between the clock input and the first output terminal.
A gate driver, comprising:
- a plurality of stages, each of the stages including:
- a clock input configured to receive a shift clock signal;
- an output terminal configured to supply an output voltage to another stage of the gate driver;
- a pull-up transistor having a first electrode coupled to the clock input, a second electrode coupled to the output terminal, and a gate terminal coupled to a Q node;
- a first pull-down transistor having a first electrode coupled to a low supply voltage, a second electrode coupled to the output terminal, and a gate electrode coupled to a first QB node;
- a second pull-down transistor having a first electrode coupled to the low supply voltage, a second electrode coupled to the output terminal, and a gate electrode coupled to a second QB node;
- and
- a diode coupled between the clock input and the output terminal.
Dependencies are inferred from the claim text.