Shift register

A shift register having a configuration in which a plurality of unit circuits are connected in multi-stage, wherein

• the unit circuit comprises:
• an output transistor having a first conduction terminal connected to a clock terminal configured to input a clock signal, a second conduction terminal connected to an output terminal configured to output the clock signal, and a control terminal connected to a first node;
• an output reset transistor having a first conduction terminal connected to the output terminal, a second conduction terminal to which an off potential is applied, and a control terminal connected to a second node;
• and
• a node control unit configured to control potentials of the first and second nodes,
• the node control unit includes a node stabilization transistor having a first conduction terminal connected to the second node, a second conduction terminal to which the off potential is applied, and a control terminal connected to the output terminal, and
• the unit circuit further comprises an output initialization transistor having a first conduction terminal connected to the output terminal, a second conduction terminal to which the off potential is applied, and a control terminal to which an initialization signal that becomes an on level when performing an initialization is supplied.