US 2018/0122318 A1 · GATE DRIVING CIRCUIT

a plurality of GOA unit circuits, wherein respective odd stage GOA unit circuits are cascade connected, and respective even stage GOA unit circuits are cascade connected;

signal lines respectively employed for providing an odd stage first scan control signal, an odd stage second scan control signal, an odd stage scan start signal, an odd stage first high frequency clock signal, an odd stage second high frequency clock signal, located corresponding to the odd stage GOA unit circuits;

signal lines respectively employed for providing an even stage first scan control signal, an even stage second scan control signal, an even stage scan start signal, an even stage first high frequency clock signal, an even stage second high frequency clock signal, located corresponding to the even stage GOA unit circuits;

a common signal line, employed for providing a first low frequency clock signal and a second low frequency clock signal, located corresponding to all the GOA unit circuits;

the GOA unit circuit of every stage comprises a forward-backward scan control module, a transfer regulation module, an output module, a first pull-down module and a pull-down holding module;

the forward-backward scan control module further comprises a first controlling module, and a second controlling module, and the first controlling module functions for pull-up control in forward scan, and functions for pull-down in backward scan;

the second controlling module functions for pull-up control in backward scan, and functions for pull-down in forward scan;

N is set to be a positive integer and except the GOA unit circuits of the first, the second, the next to last and the last stages, in the Nth stage GOA unit circuit:

the first controlling module comprises:

an eleventh transistor, and a gate of the eleventh transistor is electrically coupled to a stage transfer signal of the N−2th stage GOA unit circuit, and a drain is electrically coupled to a first node, and as N is an odd number, a source is electrically coupled to the odd stage first scan control signal, and as N is an even number, the source is electrically coupled to the even stage first scan control signal;

the second controlling module comprises:

a forty-first transistor, and a gate of the forty-first transistor is electrically coupled to a stage transfer signal of the N+2th stage GOA unit circuit, and a drain is electrically coupled to the first node, and as N is an odd number, a source is electrically coupled to the odd stage second scan control signal, and as N is an even number, the source is electrically coupled to the even stage second scan control signal;

the output module comprises:

a twenty-first transistor, and a gate of the twenty-first transistor is electrically coupled to the first node, and a drain outputs a scan signal, and as N is an odd number, a source is electrically coupled to the odd stage first high frequency clock signal, and as N is an even number, the source is electrically coupled to the even stage first high frequency clock signal;

a twenty-second transistor, and a gate of the twenty-second transistor is electrically coupled to the first node, and a drain outputs a stage transfer signal, and as N is an odd number, a source is electrically coupled to the odd stage first high frequency clock signal, and as N is an even number, the source is electrically coupled to the even stage first high frequency clock signal;

a capacitor, and one end of the capacitor is electrically coupled to the first node, and the other end is electrically coupled to the stage transfer signal;

the pull-down holding module comprises:

a fifty-fifth transistor, a first pull-down holding module and a second pull-down holding module;

a gate of the fifty-fifth transistor is electrically coupled to the first node, and a source is electrically coupled to a second node, and a drain is electrically coupled to a third node;

the first pull-down holding module comprises:

a thirty-third transistor, and a gate of the thirty-third transistor is electrically coupled to the second node, and a source is electrically coupled to the scan signal, and a drain is electrically coupled to a constant low voltage level;

a thirty-sixth transistor, and a gate of the thirty-sixth transistor is electrically coupled to the second node, and a source is electrically coupled to the stage transfer signal, and a drain is electrically coupled to the constant low voltage level;

a forty-third transistor, and a gate of the forty-third transistor is electrically coupled to the second node, and a source is electrically coupled to the first node, and a drain is electrically coupled to the constant low voltage level;

a fifty-first transistor, and both a gate and a source of the fifty-first transistor are electrically coupled to the first low frequency clock signal, and a drain is electrically coupled to a gate of a fifty-third transistor;

the fifty-third transistor, and the gate of the fifty-third transistor is electrically coupled to the drain of the fifty-first transistor, and a source is electrically coupled to the first low frequency clock signal, and a drain is electrically coupled to the second node;

a fifty-fourth transistor, and a gate of the fifty-fourth transistor is electrically coupled to the second low frequency clock signal, and a source is electrically coupled to the first low frequency clock signal, and a drain is electrically coupled to the second node;

the second pull-down holding module comprises a thirty-second transistor, and a gate of the thirty-second transistor is electrically coupled to the third node, and a source is electrically coupled to the scan signal, and a drain is electrically coupled to the constant low voltage level;

a thirty-fifth transistor, and a gate of the thirty-fifth transistor is electrically coupled to the third node, and a source is electrically coupled to the stage transfer signal, and a drain is electrically coupled to the constant low voltage level;

a forty-second transistor, and a gate of the forty-second transistor is electrically coupled to the third node, and a source is electrically coupled to the first node, and a drain is electrically coupled to the constant low voltage level;

a sixty-first transistor, and both a gate and a source of the sixty-first transistor are electrically coupled to the second low frequency clock signal, and a drain is electrically coupled to a gate of a sixty-third transistor;

the sixty-third transistor, and the gate of the sixty-third transistor is electrically coupled to the drain of the sixty-first transistor, and a source is electrically coupled to the second low frequency clock signal, and a drain is electrically coupled to the third node;

a sixty-fourth transistor, and a gate of the sixty-fourth transistor is electrically coupled to the first low frequency clock signal, and a source is electrically coupled to the second low frequency clock signal, and a drain is electrically coupled to the third node;

the transfer regulation module comprises a fifty-second transistor, and a gate of the fifty-second transistor is electrically coupled to the first node, and a source is electrically coupled to the second node, and a drain is electrically coupled to the constant low voltage level;

a sixty-second transistor, and a gate of the sixty-second transistor is electrically coupled to the first node, and a source is electrically coupled to the third node, and a drain is electrically coupled to the constant low voltage level;

a tenth transistor, and a gate of the tenth transistor is electrically coupled to the stage transfer signal of the N+2th stage GOA unit circuit, and a drain is electrically coupled to the second node, and as N is an odd number, a source is electrically coupled to the odd stage first scan control signal, and as N is an even number, the source is electrically coupled to the even stage first scan control signal;

a twelfth transistor, and a gate of the twelfth transistor is electrically coupled to the stage transfer signal of the N+2th stage GOA unit circuit, and a drain is electrically coupled to the third node, and as N is an odd number, a source is electrically coupled to the odd stage first scan control signal, and as N is an even number, the source is electrically coupled to the even stage first scan control signal;

a fifty-sixth transistor, and a gate of the fifty-sixth transistor is electrically coupled to the stage transfer signal of the N−2th stage GOA unit circuit, and a source is electrically coupled to the drain of the fifty-first transistor and the second node, and as N is an odd number, a drain is electrically coupled to the odd stage second scan control signal, and as N is an even number, the drain is electrically coupled to the even stage second scan control signal;

a sixty-sixth transistor, and a gate of the sixty-sixth transistor is electrically coupled to the stage transfer signal of the N−2th stage GOA unit circuit, and a source is electrically coupled to the drain of the sixty-first transistor and the third node, and as N is an odd number, a drain is electrically coupled to the odd stage second scan control signal, and as N is an even number, the drain is electrically coupled to the even stage second scan control signal;

the first pull-down module comprises a thirty-first transistor, and a source is electrically coupled to the scan signal, and a drain is electrically coupled to the constant low voltage level, and as N is an odd number, a gate of the thirty-first transistor is electrically coupled to the odd stage second high frequency clock signal, and as N is an even number, the gate of the thirty-first transistor is electrically coupled to the even stage second high frequency clock signal;

the first low frequency clock signal and the second low frequency clock signal are inverse in phase;

as N is an odd number, in the N+2th stage GOA unit circuit, both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the odd stage second high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the odd stage first high frequency clock signal;

as N is an even number, in the N+2th stage GOA unit circuit, both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the even stage second high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the even stage first high frequency clock signal;

as the odd stage first scan control signal is high voltage level and the odd stage second scan control signal is low voltage level, the odd stage GOA unit circuits are controlled to perform forward scan;

as the odd stage first scan control signal is low voltage level and the odd stage second scan control signal is high voltage level, the odd stage GOA unit circuits are controlled to perform backward scan;

as the even stage first scan control signal is high voltage level and the even stage second scan control signal is low voltage level, the even stage GOA unit circuit is controlled to perform forward scan;

as the even stage first scan control signal is low voltage level and the even stage second scan control signal is high voltage level, the even stage GOA unit circuit is controlled to perform backward scan;

wherein in the first stage connection of the gate driving circuit, all the gate of the eleventh transistor, the gate of the fifty-sixth transistor, and the gate of the sixty-sixth transistor are electrically coupled to the odd stage scan start signal;

both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the odd stage first high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the odd stage second high frequency clock signal;

in the second stage connection of the gate driving circuit, all the gate of the eleventh transistor, the gate of the fifty-sixth transistor, and the gate of the sixty-sixth transistor are electrically coupled to the even stage scan start signal;

both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the even stage first high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the even stage second high frequency clock signal;

in the next to last stage connection of the gate driving circuit, all the gate of the forty-first transistor, the gate of the tenth transistor, and the gate of the twelfth transistor are electrically coupled to the odd stage scan start signal;

both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the odd stage second high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the odd stage first high frequency clock signal;

in the last stage connection of the gate driving circuit, all the gate of the forty-first transistor, the gate of the tenth transistor, and the gate of the twelfth transistor are electrically coupled to the even stage scan start signal;

both the source of the twenty-first transistor and the source of the twenty-second transistor are electrically coupled to the even stage second high frequency clock signal, and the gate of the thirty-first transistor is electrically coupled to the even stage first high frequency clock signal;

wherein both the odd stage first scan control signal and the even stage first scan control signal are high voltage level, and both the odd stage second scan control signal and the even stage second scan control signal are low voltage level;

in a scanning period of the frame, the odd stage scan start signal is first provided to the gate of the eleventh transistor of the first stage GOA unit circuit, and after scan to all the odd stage GOA unit circuits is accomplished, the even stage scan start signal is provided to the gate of the eleventh transistor of the second stage GOA unit circuit;

the forward scan of the odd stage GOA unit circuits and the forward scan of the even stage GOA unit circuits are performed in time division.

Gate driving circuit

Life of this patent

Gate driving circuit

Life of this patent

Abstract

Claims12