Display driving device
AssigneeSilicon Works Co., Ltd.
InventorsYoung Bok Kim, Taiming Piao, Hyun Kyu Jeon, Joon Ho Na
Life of this patent
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Abstract
Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.
Claims15
A display driving device comprising:
- a first digital-to-analog converter (DAC) configured to output a first grayscale voltage selected in response to first digital data as a first DAC signal;
- a second DAC configured to output a second grayscale voltage selected in response to second digital data as a second DAC signal, wherein the first digital data and the second digital data are alternately inputted;
- and
- an output buffer comprising a first input terminal to which the first DAC signal is loaded and a second input terminal to which the second DAC signal is loaded, and configured to output a source driving signal by selecting a DAC signal loaded at a preset level or more between the first and second DAC signals which are loaded at different time points.
A display driving device comprising:
- a first output unit configured to output a first source driving signal in the range of a first supply voltage to a second supply voltage;
- a second output unit configured to output a second source driving signal in the range of the second supply voltage to a third supply voltage;
- and
- a multiplexer configured to control paths through which the first and second source driving signals are outputted to a display panel,
- wherein the first output unit comprises:
- a first DAC configured to output a first grayscale voltage selected in response to first digital data as a first DAC signal;
- a second DAC configured to output a second grayscale voltage selected in response to second digital data as a second DAC signal;
- and
- a first output buffer comprising a first input terminal to which the first DAC signal is loaded and a second input terminal to which the second DAC signal is loaded, and configured to output the first source driving signal by selecting a DAC signal loaded at a preset level or more between the first and second DAC signals which are loaded at different time points,
- wherein the second output unit comprises:
- a third DAC configured to output a third grayscale voltage selected in response to third digital data as a third DAC signal;
- a fourth DAC configured to output a fourth grayscale voltage selected in response to fourth digital data as a fourth DAC signal;
- and
- a second output buffer comprising a third input terminal to which the third DAC signal is loaded and a fourth input terminal to which the fourth DAC signal is loaded, and configured to output the second source driving signal by selecting a DAC signal loaded at the preset level or more between the third and fourth DAC signals which are loaded at different time points.
Dependencies are inferred from the claim text.