Systems and methods for preventing data remanence in memory systems
AssigneeAltera Corporation
InventorsBruce B. Pedersen, Dirk A. Reese
Life of this patent
Estimating the term…
Abstract
Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.
Claims20
A circuit comprising:
- a first memory comprising:
- a data input;
- a data output signal;
- and
- a complemented data output signal;
- a second memory comprising:
- a data input;
- a data output signal;
- and
- a complemented data output signal;
- and
- exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
- selection circuitry that uses a load signal to select between an input signal to the circuit or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal;
- and
- interconnection circuitry that couples the complemented data output signal of the second memory to the data input of the second memory.
A circuit comprising:
- a first memory comprising:
- a data input;
- a data output signal;
- and
- a complemented data output signal;
- a second memory comprising:
- a data input;
- a data output signal;
- and
- a complemented data output signal;
- and
- exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
- selection circuitry that uses a load signal to select between an input signal to the circuit or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal and the selection circuitry loads the input signal to the circuit into the first memory in response to the load signal;
- and
- interconnection circuitry that:
- couples the complemented data output signal of the second memory to the data input of the second memory;
- couples the load signal to a reset of the second memory that resets the data output signal of the second memory to a reset value;
- and
- couple the selection circuit output signal to data input of the first memory.
A field-programmable gate array (FPGA) comprising:
- a first memory comprising:
- a data input;
- a data output signal;
- and
- a complemented data output signal;
- a second memory comprising:
- a data input;
- a data output signal;
- a reset port that resets in response to a load signal;
- and
- a complemented data output signal;
- and
- exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
- selection circuitry that uses the load signal to select between an input signal to the circuit or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal;
- and
- interconnection circuitry that couples the complemented data output signal of the second memory to the data input of the second memory.
Dependencies are inferred from the claim text.