US 2018/0121675 A1 · PROVIDING LOGICAL PARTITIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE

Abstract

Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Claims20

Dependent claims

A method of providing hardware thread-specific status information in a multi-threaded processor executing multiple logical partitions, the method comprising:

maintaining the hardware thread specific status information in a register within the multi-threaded processor;
detecting access to the hardware thread-specific status information by a currently-executing process;
determining a privilege level of the currently-executing process;
and
responsive to determining that the privilege level of the currently-executing process corresponds to a process within a given one of the multiple logical partitions to which less than all of the hardware threads supported by the processor are assigned, transforming the hardware thread-specific status information in a manner that appears as exclusive use of the processor by threads of the given logical partition, while a number of hardware threads of the processor are assigned to another logical partition other than the given logical partition.

2 more elements

A computer program product comprising a computer-readable storage medium storing program instructions for execution by a computer system, wherein the program instructions are program instructions of a hypervisor for managing multiple logical partitions executing within a processor core, wherein the program instructions comprise:

program instructions of an interrupt handler to, responsive to a trap interrupt generated upon access to a register containing hardware-thread specific information, transform the hardware thread-specific information in the register to simulate the exclusive use of the processor core by a given partition to generate a logical register value that is different than the actual value in the register;
and
program instructions of the interrupt handler to replace a return value for the access to the hardware thread-specific information with the logical register value.

A computer system comprising:

a memory for storing program instructions and data values;
and
a processor coupled to the memory for executing the program instructions, wherein the processor maintains hardware thread-specific status information for hardware threads supported by the processor in a register within the processor, wherein the program instructions are program instructions of a hypervisor for managing multiple logical partitions executing within the processor, wherein the program instructions comprise program instructions of an interrupt handler to, responsive to a trap interrupt generated upon access to a register containing hardware-thread specific information, transform the hardware thread-specific information in the register to simulate the exclusive use of the processor core by a given partition to generate a logical register value that is different than the actual value in the register, and program instructions of the interrupt handler to replace a return value for the access to the hardware thread-specific information with the logical register value.

Dependencies are inferred from the claim text.

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Life of this patent

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Life of this patent

Abstract

Claims20