DRC Processing Tool For Early Stage IC Layout Designs

A design rule checking (DRC) tool configured to performed DRC processing that identifies layout errors in an early-stage integrated circuit (IC) layout design corresponding to an IC device by analyzing said early-stage IC layout design using a plurality of rules, and by generating error information suitable for correcting the layout errors, thereby facilitating the efficient generation of a finished layout design that is suitable for producing masks used in the fabrication of the IC device, the DRC tool comprising:

• means for generating a design layout workspace including a plurality of designated cells that collectively define said early-stage IC layout design;
• and
• means for performing a plurality of rule check processes, each rule check process including analyzing a selected current cell of said plurality of designated cells in said design layout workspace using a sequentially selected current rule of said plurality of rules, and recording an associated rule violation when said selected current cell violates said selected current rule, wherein performing said plurality of rule check processes includes sequentially selecting said current rule from said plurality of rules such that a first said rule check process is performed using a first rule of said plurality of rules as a selected first said current rule on at least some of the cells in said design layout workspace, and then a second rule check process is performed using a second rule of said plurality of rules as a selected second said current rule,
• wherein said means for performing a plurality of rule check processes includes means for terminating said first rule check process when a first rate of rule violations of said selected first current rule exceeds a predetermined maximum error rate value, and for initiating said second rule check process using said selected second current rule before at least some of said cells in said design layout workspace have been checked using said selected first current rule.

A design rule checking (DRC) tool configured to performed DRC processing that identifies layout errors in an early-stage integrated circuit (IC) layout design corresponding to an IC device by analyzing said early-stage IC layout design using a plurality of rules, and by generating error information suitable for correcting the layout errors, thereby facilitating the efficient generation of a finished layout design that is suitable for producing masks used in the fabrication of the IC device, the DRC tool comprising:

• means for generating a design layout workspace including a plurality of designated cells that collectively define said early-stage IC layout design;
• means for identifying removing from said design layout workspace one or more problematic cells of said plurality of designated cells, each said problematic cell being characterized by having associated size and location data that violates one or more cell placement rules, whereby said design layout workspace includes a remaining plurality of cells after removal of said one or more problematic cells;
• means for performing a plurality of first-pass rule check processes, each said first-pass rule check process including analyzing a current cell selected only from said remaining plurality of remaining cells in said design layout workspace using a selected current rule of said plurality of rules, and recording an associated rule violation when said selected current cell violates said selected current rule;
• and
• means for generating said error information upon termination of said rule check processing, said error information including first error data indicating each said rule violation occurring during said plurality of first-pass rule check processes, and said error information also including second error data identifying the erroneous placement of each of said one or more problematic cells.

A design rule checking (DRC) tool configured to performed DRC processing that identifies layout errors in an early-stage integrated circuit (IC) layout design corresponding to an IC device by analyzing said early-stage IC layout design using a plurality of rules, and by generating error information suitable for correcting the layout errors, thereby facilitating the efficient generation of a finished layout design that is suitable for producing masks used in the fabrication of the IC device, wherein each cell of said associated plurality of cells is characterized by associated location data identifying a relative X-Y location of said each cell of said plurality of cells, the DRC tool comprising:

• means for generating a design layout workspace including a plurality of designated cells that collectively define said early-stage IC layout design;
• means for performing a plurality of rule check processes, each rule check process including analyzing a selected current cell of said plurality of designated cells in said design layout workspace using a sequentially selected current rule of said plurality of rules, and recording an associated rule violation when said selected current cell violates said selected current rule, wherein performing said plurality of rule check processes includes sequentially selecting said current rule from said plurality of rules such that a first said rule check process is performed using a first rule of said plurality of rules as a selected first said current rule on at least some of the cells in said design layout workspace, and then a second rule check process is performed using a second rule of said plurality of rules as a selected second said current rule, and
• means for generating said error information upon termination of said plurality of rule check processes such that said error information includes graphic error data depicting each designated cell having at least one said rule violation by a corresponding dot, each said corresponding dot being relatively positioned at an X-Y location corresponding to the relative X-Y location of said corresponding designated cell.

A design rule checking tool for identifying layout errors in an early-stage integrated circuit (IC) layout design corresponding to an IC device, and for providing error information suitable for correcting the layout errors and producing a modified layout design suitable for producing masks used in the fabrication of the IC device, the design rule checking tool comprising:

• means for writing the early-stage integrated circuit (IC) layout design into a design rule check (DRC) workspace including a plurality of layers, each said layer including a plurality of cells, wherein said plurality of cells and plurality of layers define said early-stage IC layout design;
• means for identifying and marking previously analyzed cells in a selected layer of the plurality of layers such that previously un-analyzed cells in the selected layer remain unmarked;
• and
• means for performing DRC processing on the selected layer such that said DRC processing is only performed on said unmarked cells.