Vertical transistors with merged active area regions
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Albert M. Chu, Terence B. Hook, Seong-Dong Kim
Life of this patent
Estimating the term…
Abstract
A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.
Claims19
A method for device layout with vertical transistors, comprising:
- identifying active area regions in a layout of a semiconductor device with vertical transistors;
- determining sets of adjacent active area regions having a same electrical potential;
- prioritizing the sets of adjacent active area regions to be merged based upon one or more performance criterion;
- and
- merging the sets of adjacent active area regions to form larger active area regions according to a priority.
A non-transitory computer readable storage medium comprising a computer readable program for device layout with vertical transistors, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
- identifying active area regions in a layout of a semiconductor device with vertical transistors;
- determining sets of adjacent active area regions having a same electrical potential;
- prioritizing the sets of adjacent active area regions to be merged based upon one or more performance criterion;
- and
- merging the sets of adjacent active area regions to form larger active area regions according to a priority.
Dependencies are inferred from the claim text.