Graph based dynamic timing and activity analysis
AssigneeRegents of the University of Minnesota
InventorsHari Cherupalli, John Sartori
Life of this patent
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Abstract
A method for analyzing a digital circuit includes performing a hardware simulation for a workload on a digital circuit design to generate an activity file including a plurality of time stamps and a list of gates, nets, pins, or cells that toggled at each corresponding time stamp. The method includes generating a toggled-set for each time stamp in the activity file and analyzing a vertex-induced sub-graph defined by each toggled-set. The method includes determining a characteristic of the digital circuit design over a specified time window based on the analysis of each toggled-set.
Claims20
A method for analyzing a digital circuit, the method comprising:
- performing a hardware simulation for a workload on a digital circuit design to generate an activity file including a plurality of time stamps and a list of gates, nets, pins, or cells that toggled at each corresponding time stamp;
- generating a toggled-set for each time stamp in the activity file;
- analyzing a vertex-induced sub-graph defined by each toggled-set;
- and
- determining a characteristic of the digital circuit design over a specified time window based on the analysis of each toggled-set.
A method to report a predetermined number of worst exercised paths of a digital circuit, the method comprising:
- performing a hardware simulation for a workload on a digital circuit design to generate an activity file including a plurality of time stamps and a list of gates, nets, pins, or cells that toggled at each corresponding time stamp;
- generating a toggled-set for each time stamp in the activity file;
- and
- determining the predetermined number of worst exercised paths based on the toggled-sets.
Dependencies are inferred from the claim text.