US 2018/0121574 A1 · Method, Apparatus And System For Automatically Performing End-To-End Channel Mapping For An Interconnect

Abstract

In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

Claims20

Dependent claims

A machine-readable medium having stored thereon instructions, which if performed by a design tool cause the design tool to perform a method comprising:

receiving, in the design tool, communication profile information regarding a system on chip (SoC) undergoing a design process, the SoC to comprise a plurality of intellectual property (IP) logics to be interconnected by a fabric including a plurality of fabric segments, the communication profile information including, at least, source channel information for a source IP logic and sink channel information for a sink IP logic;
performing a channel mapping between the source IP logic and the sink IP logic through the plurality of fabric segments according to the communication profile information;
and
updating a data structure based on the channel mapping, to form an intermediate representation of at least a portion of the SoC.

1 more element

Dependencies are inferred from the claim text.

Method, Apparatus And System For Automatically Performing End-To-End Channel Mapping For An Interconnect

Life of this patent

Method, Apparatus And System For Automatically Performing End-To-End Channel Mapping For An Interconnect

Life of this patent

Abstract

Claims20