Symmetric block sparse matrix-vector multiplication
AssigneeNVIDIA Corporation
InventorSteve RENNICH
Life of this patent
Estimating the term…
Loading patent…
AssigneeNVIDIA Corporation
InventorSteve RENNICH
Estimating the term…
Embodiments of the present invention are directed to methods and systems for performing block sparse matrix-vector multiplications with improved efficiency through the use of a specific re-ordering the matrix data such that matrix symmetry can be exploited while simultaneously avoiding atomic memory operations or the need for inefficient memory operations in general. One disclosed method includes reordering the matrix data such that, for any column of non-transpose data, and for any row of transpose data simultaneously processed within a single thread-block on a GPU, all matrix elements update independent elements of the output vector. Using the method, the amount of data required to represent the sparse matrix can be reduced by as much as 50%, thereby doubling the effective performance on the GPU, and doubling the size of the matrix that can be accelerated by the GPU.
A method for performing block sparse matrix calculations on a symmetric portion of a block sparse matrix, the method comprising:
A computing device, comprising:
A non-transitory computer readable medium comprising a plurality of programmed instructions, which when executed by a processor in a computing device is operable to perform block sparse matrix calculations, the programmed instructions comprising:
The computer readable medium according to claim 21, wherein the instructions to re-arrange comprise instructions to allocate a matrix block of the plurality of matrix blocks to an SM of the plurality of SMs to be processed as a thread block comprising a plurality of threads.
Dependencies are inferred from the claim text.