Super single instruction multiple data (super-simd) for graphics processing unit (gpu) computing

A compute unit (CU), the CU comprising:

• a plurality of super single instruction, multiple data execution units (SIMDs), each super-SIMD including:
• a plurality of vector general purpose registers (VGPRs) grouped in sets;
• a plurality of first arithmetic logic units (ALUs), each first ALU coupled to one set of the plurality of VGPRs;
• a plurality of second ALUs, each second ALU coupled to one set of the plurality of VGPRs;
• and
• a plurality of destination caches (Do$s), each Do$ coupled to one first ALU and one second ALU and receiving an output of the one first ALU and one second ALU;
• a plurality of texture units (TATDs) coupled to at least one of the plurality of super-SIMDs;
• an instruction scheduler (SQ) coupled to each of the plurality of super-SIMDs and the plurality of TATDs;
• a local data storage (LDS) coupled to each of the plurality of super-SIMDs, the plurality of TATDs, and the SQ;
• and
• a plurality of L1 caches, each of the plurality uniquely coupled to one of the plurality of TATDs.

A small compute unit (CU), the CU comprising:

• two super single instruction, multiple data (SIMDs), each super-SIMD including:
• a plurality of vector general purpose registers (VGPRs) grouped into sets of VGPRs;
• a plurality of first arithmetic logic units (ALUs), each first ALU coupled to one set of the plurality of VGPRs;
• a plurality of second ALUs, each second ALU coupled to one set of the plurality of VGPRs;
• and
• a plurality of destination caches (Do$s), each Do$ coupled to one first ALU of the plurality of first ALUs and one second ALU of the plurality of second ALUs and receiving an output of the one first ALU and one second ALU;
• a texture address/texture data units (TATD) coupled to the super-SIMDs;
• an instruction scheduler (SQ) coupled to each of the super-SIMDs and the TATD;
• a local data storage (LDS) coupled the super-SIMDs, the TATD, and the SQ;
• and
• an L1 cache coupled to the TATD.

A method executing instructions in a super single instruction, multiple data execution unit (SIMD), the method comprising:

• generating instructions using instruction level parallel optimization;
• allocating wave slots for the super-SIMD with a PC for each wave;
• selecting a VLIW2 instruction from a highest priority wave;
• reading a plurality of vector operands in the super-SIMD;
• checking a plurality of destination operand caches (Do$s) and mark the operands able to be fetched from Do$;
• scheduling a register file and read the Do$ to execute the VLIW2 instruction;
• and
• updating the PC for the selected waves.