System Arbiter with Programmable Priority Levels

An embedded controller comprising:

• a system bus;
• a central processing unit (“CPU”) communicatively coupled to the system bus, the central processing unit comprising a CPU priority register, and the central processing unit operable to access the system according to a plurality of operating modes;
• a plurality of arbiter clients communicatively coupled to the system bus, each of the plurality of arbiter clients comprising a programmable priority register;
• and
• a programmable system arbiter for granting access to the system bus among the plurality of arbiter clients and the central processing unit, the programmable system arbiter communicatively coupled to the plurality of arbiter clients and the system bus and the central processing unit, wherein:
• the programmable system arbiter comprises one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type;
• and
• the programmable system arbiter is operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of the plurality of operating modes, and each of the one or more interrupt types.