US 2018/0121376 A1 · MEMORY DEVICE SUPPORTING RANK-LEVEL PARALLELISM AND MEMORY SYSTEM INCLUDING THE SAME

Abstract

A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

Claims20

Dependent claims

A memory system comprising:

a memory controller;
a plurality of ranks;
and
a rank shared bus configured to couple the memory controller and the plurality of ranks,
wherein each of the plurality of ranks comprises:
a plurality of banks;
a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer;
and
the intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal output from the memory controller.

6 more elements

A memory system comprising one or more of memory modules coupled to a memory controller through a channel, each of the one or more of memory modules comprising a plurality of ranks, each of the plurality of ranks comprising a plurality of memory devices, wherein each of the plurality of memory devices comprises:

a cell region;
a row control circuit configured to control a row operation of the cell region;
a column control circuit configured to control a column operation of the cell region;
a command decoder configured to process a command provided from the memory controller and to control the row control circuit and the column control circuit;
a data transceiver configured to transmit/receive data to/from the channel according to control of the command decoder;
and
an intermediate buffer configured to communicate with the column control circuit or the data transceiver according to a first plurality of control signals from the command decoder.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/628,960Filed 21 Jun 2017

Priority

KR 10-2016-01441511 Nov 2016

Published

3 May 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 13/1647
Based on arbitration: with interleaved bank access
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 12/0284
User address space allocation, e.g. contiguous or non contiguous base addressing: multiple user address space allocation, e.g. using different…
G06F 13/36
Handling requests for interconnection or transfer: for access to common bus or bus system

Memory device supporting rank-level parallelism and memory system including the same

Life of this patent

Memory device supporting rank-level parallelism and memory system including the same

Life of this patent

Abstract

Claims20