Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register

A memory device for storing data, the memory device comprising:

• a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells;
• a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank;
• and
• a cache memory associated with each of the plurality of memory banks and each of the plurality of pipelines, and wherein the cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of the associated memory bank.

A memory device for storing data, the memory device comprising:

• a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells, wherein the addressable memory cells of an associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;
• a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank;
• and
• a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.