Structures of bottom select transistor for embedding 3d-nand in beol and methods

A method of manufacturing a flash memory device, comprising:

• providing a substrate;
• forming an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer;
• forming a plurality of sacrificial layers alternating with a plurality of spacer insulator layers on the electrode layer;
• etching the sacrificial layers and the spacer insulator layers to form a through hole exposing a surface of the electrode layer;
• forming a channel structure in the through hole comprising, from an inside to an outside, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding a surface of the channel layer, a charge trapping layer surrounding a surface of the tunneling insulator layer, and a barrier layer surrounding a surface of the charge trapping layer;
• removing the sacrificial layers to form a plurality of voids;
• and
• forming a plurality of gate structures in the plurality of voids.