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US 2018/0121287 A1Published application
Inline error detection and correction techniques
AssigneeNVIDIA Corporation
InventorsMichael Wasserman, Manas Mandal, Steven Molnar, Jay Gupta, James M. Van Dyke, John Welsford Brooks
Life of this patent
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Abstract
In accordance with embodiments of the present technology, region based selective error detection and correction techniques provide for the tradeoff between the safety of error detection and error correction (EDEC) protection, and the higher bandwidth and capacity of non-EDEC protection for different uses.
Claims16
A method comprising:
- receiving a memory transaction with a given address;
- determining an EDEC control state;
- determining an adjusted address based upon the given address;
- determining an EDEC address based upon the given address;
- calculating EDEC codes, if the EDEC control state is enabled and the memory transaction is a write;
- storing the data in memory at the adjusted address, if the memory transaction is a write;
- and
- storing the EDEC codes in the memory at the EDEC address, if the EDEC control state is enabled and the memory transaction is a write.
5 more elements
A method comprising:
- receiving a memory transaction with a given address;
- determining an EDEC control state;
- determining an adjusted address based upon the given address of the memory transaction, if the EDEC control state is enabled;
- determining an EDEC address based upon the given address, if the EDEC control state is enabled;
- reading from memory at the adjusted address, if the memory transaction is a read;
- reading the EDEC codes, corresponding to the data, from memory at the EDEC address, if the EDEC control state is enabled and the memory transaction is the read;
- applying an EDEC algorithm using the EDEC codes to detect if there are one or more detectable errors in the data read from the memory;
- outputting the data read from memory, if the EDEC control state is disabled and the memory transaction is the read;
- outputting each word of data if no errors are detected in the corresponding word and the memory transaction is the read;
- and
- invoking an operation to process each error detected by the EDEC algorithm if the EDEC control state is enabled and the memory transaction is a read.
8 more elements
Dependencies are inferred from the claim text.