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US 2018/0121283 A1Published application
Enhanced Memory Reliability in Stacked Memory Devices
AssigneeInvensas Corporation
InventorWilliam C. Plants
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Abstract
The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.
Claims12
A memory device comprising:
- (A) a controller integrated circuit (IC), further comprising:
- (i) an external data bus,
- (ii) a write logic circuit coupled to the external data bus, and
- (iii) a read logic circuit coupled to the external data bus;
- (B) a plurality of data memory integrated circuits (ICs) coupled to the write logic circuit and to the read logic circuit;
- and
- (C) a parity memory IC coupled to the write logic circuit and to the read logic circuit.
4 more elements
A memory device, comprising:
- (A) a base logic die, further comprising:
- (i) an external write data bus,
- (ii) an external read data bus,
- (iii) a write logic circuit coupled to the external data bus, and
- (iv) a read logic circuit coupled to the external data bus;
- (B) at least three memory integrated circuits coupled to both the write logic circuit and the read logic circuit, wherein:
- a RAID-style parity scheme performs error correction on data written to the device when the data is subsequently read from the device.
4 more elements
Dependencies are inferred from the claim text.