Low power memory systems

A memory device, comprising:

• an array comprising:
• a plurality of static random access memory (SRAM) cells;
• a plurality of non-volatile memory (NVM) arrays, each NVM array having a plurality of NVM cells associated with a corresponding SRAM cell, wherein
• a set of NVM cells of each NVM array are connected to a pair of bitlines through a pair of passing transistors of the corresponding SRAM cell,
• another set of NVM cells across the plurality of NVM arrays form rows of the memory device corresponding to respective word lines, and
• each of the NVM cells is enabled to exchange data with the corresponding SRAM cell by selection of the respective word line.

A method to operate a multi-bit non-volatile static random access memory (mNVSRAM) device, the method comprising:

• facilitating a data transfer between a static random access memory (SRAM) cell and one or more non-volatile memory (NVM) cells in an NVM array coupled to the SRAM cell by selecting a different word line, wherein selecting the different word line controls a connection between SRAM bitlines (BLs) and NVM BLs through a pair of inside latch nodes of the SRAM cell;
• reading the data from the NVM cell to the SRAM cell through a control signal;
• deactivating a switch device to disconnect the SRAM BLs from the NVM BLs;
• and
• writing the data from SRAM cell to the NVM cell.