Instruction sequence buffer to enhance branch prediction efficiency
AssigneeIntel Corporation
InventorMohammad ABDALLAH
Life of this patent
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Abstract
A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.
Claims20
A method for determining reliably predicted instruction sequences for branch instructions, the method comprising:
- determining a plurality of instruction sequences, wherein each instruction sequence in the plurality of instruction sequences has been fetched at least a first threshold number of times;
- determining a branch instruction sequence from the plurality of instruction sequences that includes a plurality of branch instructions and has been correctly predicted to follow the plurality of branch instructions at least a second threshold number of times;
- storing the branch instruction sequence in a buffer;
- decoding a first branch instruction, wherein the first branch instruction is the first sequential instruction in the plurality of branch instructions;
- and
- retrieving the branch instruction sequence from the buffer for execution in response to decoding the first branch instruction.
A processor for determining reliably predicted instruction sequences for branch instructions, the processor comprising:
- a fetch module that fetches a plurality of instructions;
- a buffer that stores instruction sequences;
- a sequence predictor operable to monitor execution of instructions to determine a plurality of instruction sequences, wherein each instruction sequence in the plurality of instruction sequences has been fetched at least a first threshold number of times;
- a counter operable to determine a branch instruction sequence from the plurality of instruction sequences that includes a plurality of branch instructions and has been correctly predicted to follow the plurality of branch instructions at least a second threshold number of times, wherein the fetch module stores the branch instruction sequence in the buffer;
- and
- a decoder to decode a first branch instruction, wherein the first branch instruction is the first sequential instruction in the plurality of branch instructions,
- wherein the fetch module fetches the branch instruction sequence from the buffer for execution in response to decoding the first branch instruction.
A non-transitory machine-readable medium that stores instructions, which when executed by a processor cause the processor to:
- determine a plurality of instruction sequences, wherein each instruction sequence in the plurality of instruction sequences has been fetched at least a first threshold number of times;
- determine a branch instruction sequence from the plurality of instruction sequences that includes a plurality of branch instructions and has been correctly predicted to follow the plurality of branch instructions at least a second threshold number of times;
- store the branch instruction sequence in a buffer;
- decode a first branch instruction, wherein the first branch instruction is the first sequential instruction in the plurality of branch instructions;
- and
- retrieve the branch instruction sequence from the buffer for execution in response to decoding the first branch instruction.
Dependencies are inferred from the claim text.