Processor support for hardware transactional memory
AssigneeAdvanced Micro Devices, Inc.
InventorsJaewoong CHUNG, David S. CHRISTIE, Michael P. HOHMUTH, Stephan DIESTELHORST, Martin POHLACK, Luke YEN
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Abstract
A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
Claims17
1-22. (canceled)
An apparatus, comprising:
- a processing core of a plurality of processing cores, wherein the processing core is configured to execute a speculative region of code as a single atomic memory transaction with respect to one or more others of the plurality of processing cores, wherein an end of the speculative region is indicated by a predefined ending instruction executable by the processing core;
- wherein execution of the ending instruction by the processing core comprises causing the processing core to respond to a cache coherence message sent by another of the plurality of processing cores with a negative acknowledgement, wherein the another processing core is configured to respond to the negative acknowledgement by resending the cache coherence message.
An apparatus comprising:
- a processing core of a plurality of processing cores, wherein the processing core is configured to execute a speculative region of code comprising a plurality of program instructions as a single atomic memory transaction with respect to one or more others of the plurality of processing cores;
- wherein the processing core is configured to execute one or more of the program instructions out of program order;
- and
- wherein execution of the speculative region of code by the processing core comprises:
- storing an indication that data read by the processing core in executing one or more of the plurality of program instructions is speculative;
- and
- in response to detecting a release instruction in the speculative region, storing an indication that the data is no longer speculative.
Dependencies are inferred from the claim text.