Hardware acceleration method, compiler, and device

A hardware acceleration method, comprising:

• obtaining, by a compiler, compilation policy information and source code, wherein the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor;
• compiling, by the compiler according to the compilation policy information, a code segment in the source code into first executable code matching the first processor, and sending the first executable code to the first processor;
• and
• when receiving first execution information that is obtained by means of statistics collection by the first processor and that is of the first executable code, and determining, according to the first execution information, that a code segment corresponding to the first executable code matches the second processor, compiling the code segment corresponding to the first executable code into second executable code, and sending the second executable code to the second processor.

A compiler, comprising:

• a non-transitory computer readable medium which stores computer-executable instructions;
• and
• a processor configured to execute the computer-executable instructions to perform operations comprising:
• obtaining compilation policy information and source code, wherein the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor;
• analyzing a code segment in the source code according to the compilation policy information, and determining a first code segment belonging to the first code type or a second code segment belonging to the second code type;
• and
• compiling the first code segment into first executable code, and sending the first executable code to the first processor;
• and compiling the second code segment into second executable code, and sending the second executable code to the second processor.

A compiler, comprising:

• a non-transitory computer readable medium which stores computer-executable instructions;
• and
• a processor configured to execute the computer-executable instructions to perform operations comprising:
• obtaining compilation policy information and source code, wherein the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor;
• compiling according to the compilation policy information, a code segment in the source code into first executable code matching the first processor, and sending the first executable code to the first processor;
• and
• when receiving first execution information that is obtained by means of statistics collection by the first processor and that is of the first executable code, and determining, according to the first execution information, that a code segment corresponding to the first executable code matches the second processor, compiling the code segment corresponding to the first executable code into second executable code, and sending the second executable code to the second processor.

A device, comprising:

• a scheduling manager;
• and
• a compiler configured to obtain compilation policy information and source code, wherein the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor, analyze a code segment in the source code according to the compilation policy information, determine a first code segment belonging to the first code type or a second code segment belonging to the second code type, compile the first code segment into first executable code, compile the second code segment into second executable code, and send the first executable code and the second executable code to the scheduling manager;
• and
• the scheduling manager is configured to send the first executable code to the first processor, and send the second executable code to the second processor.