Denormalization in multi-precision floating-point arithmetic circuitry
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.
Claims20
An integrated circuit that performs an arithmetic operation of first and second floating-point numbers, comprising:
- a partial product generator that generates a partial product of the first and second floating-point numbers;
- a rounding circuit coupled to the partial product generator that generates a normalized, rounded product with a first exponent range based on the partial product;
- a normalization circuit coupled to the partial product generator that generates a normalized, unrounded product with a second exponent range that is greater than the first exponent range based on the partial product and the first and second floating-point numbers;
- and
- a multiplexer coupled to the rounding circuit and the normalization circuit that selects a product of first and second floating-point numbers among the normalized, unrounded product and the normalized, rounded product based on a control signal.
A method for performing an arithmetic operation of first and second floating-point numbers with an integrated circuit, comprising:
- generating a partial product of the first and second floating-point numbers with a partial product generator;
- using a rounding circuit to generate a first product that is normalized and rounded and has a first exponent range based on the partial product;
- using a normalization circuit to generate a second product that is normalized and unrounded and has a second exponent range that is greater than the first exponent range based on the partial product and the first and second floating-point numbers;
- and
- generating a product of first and second floating-point numbers by selecting between the first and second products based on a control signal.
A non-transitory machine readable storage medium encoded with instructions for configuring an integrated circuit that comprises a partial product generator, a normalization circuit coupled to the partial product generator, a rounding circuit coupled to the partial product generator, and a multiplexer coupled to the normalization circuit and the rounding circuit to perform an arithmetic operation of a first floating-point number having a first mantissa and a first exponent that has a first exponent range and a second floating-point number having a second mantissa and a second exponent that has the first exponent range, the instructions comprising:
- instructions to configure the partial product generator to generate a partial product of the first and second floating-point numbers;
- instructions to configure the normalization circuit to generate a normalized, unrounded product that has a second exponent range that is greater than the first exponent range based on the partial product and the first and second floating-point numbers;
- instructions to configure the rounding circuit to generate a normalized, rounded product of the first and second floating-point numbers based on the partial product;
- and
- instructions to configure the multiplexer to output a product of first and second floating-point numbers by selecting between the normalized, unrounded product and the normalized, rounded product based on a control signal.
Dependencies are inferred from the claim text.