Apparatuses and methods for single level cell caching
AssigneeMicron Technology, Inc.
InventorDaniel Doyle
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses for single level cell caching are described, According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.
Claims25
A method comprising:
- receiving, at a memory device, a first set of data to be stored in a first page of multilevel memory cells;
- storing the first set of data in a page of single level memory cells;
- storing the first set of data in the first page of the multilevel memory cells;
- receiving, at the memory device, a second set of data to be stored in a second page of the multilevel memory cells;
- and
- storing the second set of data directly in the second page of the multilevel memory cells.
An apparatus comprising:
- a memory array comprising a block of single level memory cells and a block of multilevel memory cells;
- and
- a control circuit configured to receive a first set of data to be written into the memory array, store a copy of the first set of data in a page of the block of single level memory cells, and subsequently store the first set of data in a lower page of the block of multilevel memory cells, the control circuit further configured to receive a second set of data and store the second set of data directly in an upper page of the multilevel memory cells without storing a copy of the second set of data in the page of the block of single level memory cells.
A method comprising:
- storing a first set of data in a page of single level memory cells and a lower page of multilevel memory cells;
- initiating a write operation to store a second set of data directly in an upper page of the multilevel memory cells;
- prior to completing the write operation, detecting a power loss event;
- and
- copying the first set of data from the page of single level memory cells to the lower page of the multilevel memory cells.
A method comprising:
- receiving, at a control circuit, a first set of write data;
- determining, based on a page map, whether the first set of write data is to be stored in a lower page or an upper page of a block of multilevel memory cells;
- responsive to determining that the first set of write data is to be stored in the lower page, storing the first set of write data in a page of a block of single level memory cells and the lower page of the block of multilevel memory cells;
- and
- responsive to determining that the first set of write data is to be stored in the upper page, storing the first set of write data directly in the upper page of the block of multilevel memory cells.
Dependencies are inferred from the claim text.