Memory device having a plurality of low power states
AssigneeSamsung Electronics Co., Ltd.
InventorsYeon-kyu CHOI, Ki-seok OH, Seung-jun SHIN, Hye-ran KIM
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Abstract
A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.
Claims24
A method of controlling a power state of a memory device, the method comprising:
- entering a first low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a first low power state entry command;
- and
- automatically exiting the first low power mode state based on a first low power mode exit latency time that is set in a mode register of the memory device.
A method of controlling a power state of a memory device, the method comprising:
- entering a low power mode state, in which memory cell rows are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command;
- and
- receiving at least one of an alarm signal and a low power mode exit command which instruct exit from the low power mode state,
- wherein the low power mode exit command is received after a low power mode exit latency time elapses,
- wherein the low power mode exit latency time is a time period after which the memory device automatically exits the low power mode state, and
- wherein the low power mode exit latency time is set in a mode register of the memory device.
A method of controlling a power state of a memory device, the method comprising:
- entering a low power mode state, in which memory cell rows are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command;
- receiving a trigger signal instructing transition from the low power mode state to the self-refresh mode state;
- and
- operating in the self-refresh mode state in response to the trigger signal.
(canceled)
A memory device comprising:
- a memory cell array comprising memory cell rows;
- and
- a control logic configured to control a self-refresh mode state in which the memory cell rows are refreshed, and a first low power mode state in which power consumption is lower than in the self-refresh mode state,
- wherein the control logic controls entry to the first low power mode state in response to a first low power state entry command, and control exit from the first low power mode state based on a first low power mode exit latency time set in a mode register of the memory device.
(canceled)
(canceled)
A memory device comprising:
- a memory cell array comprising memory cells;
- and
- a control logic configured to control entry into and exit from an idle state, a first low power mode state and a second low power mode state,
- wherein, in the first and second low power mode states, the memory cells are refreshed,
- wherein the memory device in the first low power mode state consumes less power than in the idle state and more power than in the second low power mode state, and
- wherein the control logic controls automatic exit from the first low power mode state to the idle state after a first time period, and automatic exit from the second low power mode state to the idle state after a second time period.
(canceled)
Dependencies are inferred from the claim text.