Forcing A Processor Into A Low Power State

A processor comprising:

• a plurality of cores to independently execute instructions, the plurality of cores including a plurality of logical processors, wherein a first logical processor of a first core is to store a hardware indicator to indicate whether the first logical processor is enabled to enter into a forced idle state;
• and
• a power controller coupled to the plurality of cores to autonomously cause the first logical processor to enter into the forced idle state when an operating system has explicitly scheduled at least one task to the first logical processor and cause the first logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor of the plurality of cores is prevented from exit from an active state and entry into the forced idle state, based on a state of the hardware indicator of the at least one other logical processor to indicate that the at least one other logical processor is not enabled to enter into the forced idle state.

A method comprising:

• autonomously communicating, from a power controller of a processor, a forced idle request for entry into a forced idle state to one or more cores of a plurality of cores of the processor when the one or more cores are executing a workload;
• and
• communicating, from the power controller, a low power state exit request to the one or more cores in the forced idle state if a first timer expires prior to the one or more cores entering into the forced idle state, the first timer expiration to indicate that at least one of the one or more cores was inhibited from entry into the forced idle state based on a forced idle state hardware indicator associated with the at least one core storing a first value to indicate that the at least one core is disabled from entry into the forced idle state.