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AssigneeIndustrial Technology Research Institute
InventorsYung-Chieh Lin, Shih-Che Lin, Chao-Hong Chen, Liang-Chia Cheng
Estimating the term…
A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.
A field programmable gate array (FPGA)-based system power estimation apparatus configured to estimate power of a target intellectual property (IP) circuit, the FPGA-based system power estimation apparatus comprising:
A field programmable gate array (FPGA)-based system power estimation method for estimating power of a target intellectual property (IP) circuit, the FPGA-based system power estimation method comprising:
Dependencies are inferred from the claim text.