Voltage regulator with enhanced power supply rejection ratio and load-transient performance

A voltage regulation circuit, comprising:

• an LDO voltage regulator (low dropout voltage regulator) comprising a first error amplifier and a power field effect transistor (FET), the first error amplifier having a first input and a second input, the second input to receive an output signal fed back from the LDO voltage regulator;
• and
• means for amplifying a voltage, the voltage amplifying means coupled to the first input of the first error amplifier, the voltage amplifying means including means for receiving the output signal fed back from the LDO voltage regulator and means for receiving a reference voltage.

A voltage regulation method in a voltage regulation device, comprising:

• transmitting a reference voltage from an inverting amplifier stage to a first input of a first error amplifier of an LDO voltage regulator (low dropout voltage regulator) when the voltage regulation device is operating in accordance with a direct current;
• and
• transmitting a different voltage from the inverting amplifier stage to the first input of the first error amplifier of the LDO voltage regulator when the voltage regulation device is operating in accordance with an alternating current.