Voltage regulator circuit and control method therefor

A voltage regulator circuit, comprising:

• a voltage regulation control integrated chip, comprising a low-dropout (LDO) regulator and a pulse width modulation (PWM) voltage regulator, wherein the LDO regulator generates a driving voltage of the PWM voltage regulator based on a power source, and the PWM voltage regulator regulates an output voltage based on an input voltage and the driving voltage;
• a first switch, receiving the input voltage, wherein an output end of the first switch is coupled to an input end of the LDO regulator;
• a second switch, receiving the output voltage, wherein an output end of the second switch is coupled to the input end of the LDO regulator;
• and
• a voltage detector, generating an output power good signal based on the output voltage and a predetermined voltage range of the output voltage,
• wherein during a startup period, the first switch is turned on and the input voltage serves as the power source of the LDO regulator, so as to generate the driving voltage required by the PWM voltage regulator, and
• after the startup period, the power source of the LDO regulator are switched from the input voltage to the output voltage based on the output power good signal by the first switch and the second switch, so as to reduce an input source voltage level of the LDO regulator,
• wherein the input voltage is greater than the output voltage.