Latency guaranteed network on chip

A network-on-chip microprocessor chip, comprising:

• a set of scratchpad memory modules;
• and
• a set of tiles arranged in a grid configuration, each tile including a processor core and a router communicatively coupled with one another, wherein:
• each processor core corresponds to and is communicatively coupled with a different scratchpad memory module of the set of scratchpad memory modules,
• each router includes a set of input ports and a set of output ports, wherein each output port includes a FIFO memory element operable to store a data packet for subsequent sending to a router of an adjacent tile,
• based on a physical destination address of a data packet, each router is operable to send one or more data packets to routers of one or more adjacent tiles or the processor core corresponding to the router, and
• each router implements a static priority routing policy in the event of a traffic condition.

A method, comprising:

• receiving, at a router via a first input port of the router, a first data packet including a data payload and a physical destination address;
• selecting, based on the physical destination address, an output port for sending the first data packet;
• determining that a second data packet received at a second input port of the router is to be sent on the output port;
• applying a static priority routing policy to determine that the second data packet has priority over the first data packet based on a priority of the second input port over the first input port;
• and
• sending the first data packet on the output port after the second data packet and any other data packets subsequently and consecutively received at the second input port are sent.